This invention relates to random number generation in a digital system.
Certain communications buses can receive and transfer 16 bits of data per clock cycle. Pseudo-random-numbers (PRNs) are conventionally generated as 8 bits per clock cycle by a linear feedback shift register (LFSR), which cannot meet the throughput requirements for a 16-bit cycle.
What is needed is a system that generates a 16-bit PRN per clock cycle, utilizing the reliable technology developed to provide 8-bit PRNs. Preferably, this approach should be flexible and allow use of a variety of characteristic equations with corresponding LFSR configurations.
These needs are met by the invention, which simultaneously generates and concatenates or interleaves two 8-bit PRNs within a single clock cycle. A first 8-bit PRN component is generated by a first eight-bit PRN device on a rising clock signal; a second 8-bit PRN component is generated on a falling clock signal of the same cycle by a second, independent eight-bit PRN device; and the two 8-bit PRN components are concatenated or interleaved to provide a 16-bit PRN that is issued for that clock cycle. The characteristic polynomials used for the first and second eight-bit PRN devices are preferably the same but may be independently chosen, as long as at least one polynomial is irreducible.